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Objective
I am not looking for a job at this moment. My particular research interests are simulation based validation: leveraging hardware accelerated simulation for efficient verification and speeding up critical EDA applications for design correctness through using modern parallel processors (multi-core, GPU & heterogeneous platforms). I also have interest in hardware accelerated simulation in general.
Education
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University of Michigan, Ann Arbor
Ph.D. Candidate in Computer Science and Engineering
Graduated May 2013
Advisor: Prof. Valeria Bertacco
Dissertation Topic: Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge
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University of Michigan, Ann Arbor
M.S. in Computer Science and Engineering
2010
Concentration: Hardware Systems
GPA: 3.72/4.0 (converted to 4.0 scale)
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Indian Institute of Technology Kharagpur
B.Tech. in Computer Science and Engineering with Honors
2007
GPA: 9.06/10.00
Work Experience
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IBM Systems, Austin - Advisory Engineer
June 2013 - Prsent
I work on verification of POWER processor systems using simulation acceleration platforms.
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University of Michigan - Graduate Student Research Assistant
May 2008 - Present
Carried out independent research and reviewed papers for major EDA and computer architecture conferences
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University of Michigan - Graduate Student Instructor
January 2012 - April 2012
Taught discussion sections and held office hours for an under-graduate level computer architecture course EECS 370.
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IBM Research Lab, Haifa - Graduate Intern
July 2011 - September 2011
Adopted an existing processor core checking solution (Instruction-By-Instruction checking) for accelerated simulation by intelligent collection of trace data. This checking solution is targeted for pre-silicon validation of upcoming IBM POWER processor design generation.
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AMD, Sunnyvale - Graduate Intern
May 2010 - August 2010
Project goal was to develop a high level power model for the fusion APU's (integrated CPU cores with a GPU on chip), which works at the granularity of driver API calls between the CPU and GPU and provides power estimate. The tool was used for design exploration.
Publications
Peer Reviewed Publication(s) with Proceedings
"Checking Architectural Outputs Instruction-By-Instruction on Acceleration Platforms"
Debapriya Chatterjee (U of M), {Anatoly Koyfman, Ronny Morad, Avi Ziv} (IBM Research Lab, Haifa) and Valeria Bertacco (U of M)
Design Automation Conference (DAC), San Francisco, CA, June 2012
"SAGA: SystemC Acceleration on GPU Architectures"
Sara Vinco (U of Verona), Debapriya Chatterjee (U of M), Valeria Bertacco (U of M) and Franco Fummi (U of Verona)
Design Automation Conference (DAC), San Francisco, CA, June 2012
"Approximating Checkers for Simulation Acceleration"
{Biruk Mammo, Debapriya Chatterjee} (U of M), {Dmitry Pidan, Amir Nahir, Avi Ziv, Ronny Morad} (IBM Research Lab, Haifa) and Valeria Bertacco (U of M)
Design Automation and Test in Europe (DATE), Dresden, Germany, March 2012
"Simulation-based Signal Selection for State Restoration in Silicon Debug"
Debapriya Chatterjee, Calvin McCarter and Valeria Bertacco
International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2011
"EQUIPE: Parallel Equivalence Checking with GP-GPUs"
Debapriya Chatterjee and Valeria Bertacco
International Conference on Computer Design (ICCD), Amsterdam, The Netherlands, October 2010
"Activity-Based Refinement for Abstraction-Guided Simulation"
Debapriya Chatterjee and Valeria Bertacco
IEEE High-Level Design Validation and Test Workshop (HLDVT), San Francisco, CA, November 2009
"Event-Driven Gate-Level Simulation with GP-GPUs"
Debapriya Chatterjee, Andrew DeOrio and Valeria Bertacco
Design Automation Conference (DAC), San Francisco, CA, July 2009
"GCS: High Performance Gate-Level Simulation with GP-GPUs"
Debapriya Chatterjee, Andrew DeOrio and Valeria Bertacco
Design Automation and Test in Europe (DATE), Nice, France, April 2009
Journal Publication(s)
"Gate-Level Simulation with GPU Computing" link to the articleDebapriya Chatterjee, Andrew DeOrio and Valeria Bertacco
ACM Transactions on Design Automation of Electronic Systems (TODAES),Volume 16, Issue 3 June 2011, pages 30:1 - 30:26
"Study of the potential of alternative crops by integration of multisource data using a neuro-fuzzy technique" link to the article
Anjan Sarkar, Arka Majumdar, Shaunak Chatterjee, Debapriya Chatterjee, Shibendu S. Ray, B. Kartikeyan
International Journal of Remote Sensing(IJRS),Volume 29, Issue 19 October 2008, pages 5479 - 5493
Book Chapter(s)
"High Performance Gate-Level Simulation with GP-GPUs" link to the book's page at Morgan KaufmanDebapriya Chatterjee, Andrew DeOrio, Valeria Bertacco
GPU Computing Gems,January 2011, Morgan Kaufman Publishers, ISBN: 9780123849885
Section 5, Chapter 23: High Performance Gate-Level Simulation with GP-GPUs, pages 343 - 364
Peer Reviewed Publication(s) without Proceedings
"Simulation-based Signal Selection for State Restoration in Silicon Debug"Debapriya Chatterjee and Valeria Bertacco
International Workshop on Logic Synthesis (IWLS), UC San Diego, CA, June 2011
"EQUIPE: Parallel equivalence checking with GP-GPUs"
Debapriya Chatterjee and Valeria Bertacco
International Workshop on Logic Synthesis (IWLS), UC Irvine, CA, June 2010
Skills
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Programming Languages
C, C++, CUDA, Verilog, VHDL, SystemVerilog, Perl, Assembly languages (RISC, x86)
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Digital design flow
Experience in digital circuit design (Verilog and VHDL) and associated tools
Simulation: Synopsys VCS, Cadence NCSim (Incisive)
Synthesis: Synopsys Design Compiler
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Verification Methodology
Experience in simulation-based verification: testbench design (SystemVerilog, e), verification methodologies (UVM)
Knowledge of formal verification
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GPGPU parallel programming
Parallelization of serial implementations, experience with CUDA, knowledge of OpenCL
Relevant Coursework
- Computer Architecture (EECS 470)
- Parallel Computer Architecture (EECS 570)
- Advanced Compilers (EECS 583)
- Computer-Aided Design Verification of Digital Systems (EECS 578)
Awards and Honors
- Was awarded NVIDIA Graduate Fellowship for year 2010-2011.
- Was awarded Departmental Graduate Fellowship at University of Michigan, EECS Department.
References
- Available on request.